1. Technical Field
The present invention relates generally to security features for integrated circuits and in particular to fusible links used to provide security for integrated circuits. Still more particularly, the present invention relates to an improved security feature for integrated circuits which employs fusible links.
2. Description of the Related Art
Integrated circuits frequently require security for data stored within the circuit such as, for example, an encryption key utilized to decipher or decode public signals like a satellite signal. Security features for integrated circuits generally either prevent data stored within the circuit from being read by an external means or prevent data from being written into the integrated circuit. Prior art mechanisms for providing security for integrated circuits include fusible links. Such devices are described, for example, in U.S. Pat. Nos. 5,270,983 and 5,309,394. Fusible links may take the form of metallic or polysilicon conductors within the integrated circuit having a narrow cross-section at a specific point. High current densities through the narrow region cause the conductor to melt and create a discontinuity in the conductor.
A prior art system for employing fusible links as a security feature is depicted in FIG. 3. Security circuit 302 includes a fusible link 304, which may be a polysilicon fusible link as described above. Input/output (I/O) pad 306 is connected to one end of fusible link 304 via signal line 308. Connected to signal line 308 is a diode connected transistor 310, arranged so that the equivalent diode cathode is connected to I/O pad 306 via signal line 308. The equivalent diode anode, the control electrode, of transistor 310 is connected to ground 312.
The other end of fusible link 304 is connected to diode connected transistor 314, which is arranged so that the equivalent diode anode is connected to fusible link 304 via signal line 316. The equivalent diode cathode of transistor 314 is connected to I/O pad 318.
Signal line 316 is also connected to pull-up resistor 320, which is connected at an opposite end to a power supply voltage, and to the input of inverter 322. The output 324 of inverter 322 is connected to a signal line within the integrated circuit (not shown) employing the fusible link as a security feature. For example, the output of inverter 322 may be connected to a WRITE-enable line within a memory.
In operation, I/O pad 306 may be utilized to control the signal line connected to inverter 322. To secure the integrated circuit, fusible link 304 is "blown" by connecting I/O pad 318 to ground and driving I/O pad 306 to a voltage of 8.5 V until the current at I/O pad 318 becomes zero. When the current at I/O pad 318 becomes zero, fusible link 304 has burned through and forms a discontinuity between signal lines 308 and 316. I/O pad 306 may thus no longer be utilized to control the signal line within the integrated circuit. Diode connected transistor 314 prevents I/O pad 318 from being utilized to control the signal line. I/O pads 306 and 318 may, however, be employed for other purposes via other connections (not shown).
Security cell 302 generally suffers a failure rate--cases in which fusible link 304 does not burn through when desired--of approximately 2 percent. For many applications, this fallout rate is unacceptable. Thus, the arrangement of security cell 302 is not attractive for integration as a security feature in such applications.
It would be desirable, therefore, to provide a security feature for integrated circuits having the benefits of the arrangement described. It would further be desirable if the failure rate were improved over the arrangement described.